1. Field of the Invention
The present invention relates to a CPU system with a peripheral LSI circuit to which an SDRAM is connected, and more particularly to a CPU system that permits the CPU to access an SDRAM connected to a peripheral LSI circuit.
2. Description of the Related Art
Some CPU systems have a peripheral LSI circuit such as a graphics LSI circuit for enabling the computer to have various functions. Such CPU systems may have a unified memory architecture to reduce the size and cost thereof. The unified memory architecture allows a memory for a peripheral LSI circuit, such as a graphics memory, and a main memory to be realized as one memory. One approach to construct a unified memory architecture is to arrange a CPU system such that the CPU is capable of accessing a memory for a peripheral LSI circuit.
As shown in FIG. 1 of the accompanying drawings, a conventional CPU system has CPU 5, peripheral LSI circuit 6, and SDRAM 7. CPU 5 serves as a main processor of the conventional CPU system. Peripheral LSI circuit 6 has wait control bus interface 61, selector 62, SDRAM interface 63, and internal circuit 64.
Wait control bus interface 61 is connected to the bus of CPU 5, and performs a read/write process in response to access from CPU 5 to peripheral LSI circuit 6. In the read/write process, wait control bus interface 61 places CPU 5 in a wait mode according to a wait control process in view of the period of time that is required for a response from SDRAM 7 to be transmitted to CPU 5. Selector 62 is a selector for relaying an exchange with wait control bus interface 61 to a selected one of SDRAM interface 63 and internal circuit 64. Specifically, when access is made from CPU 5 to SDRAM 7, selector 62 selects SDRAM interface 63, and when access is made from CPU 5 to internal circuit 64, selector 62 selects internal circuit 64. SDRAM interface 63 is connected to SDRAM 7 and receives a bus signal from and sends a bus signal to SDRAM 7.
Internal circuit 64 is a circuit for realizing the functions of peripheral LSI circuit 6, and has a structure that may differ depending on the application of peripheral LSI circuit 6. Internal circuit 64 may have a processor therein. SDRAM 7 is connected to peripheral LSI circuit 6 by SDRAM interface 63, and can be accessed from CPU 5 via peripheral LSI circuit 6.
In the conventional CPU system shown in FIG. 1, peripheral LSI circuit 6 with the wait control general-purpose bus performs the wait control process in view of the period of time that is required for a response from SDRAM 7 to be transmitted to CPU 5, and allows CPU 5 to access SDRAM 7 that is connected to peripheral LSI circuit 6.
FIG. 2 of the accompanying drawings shows another conventional CPU system. The conventional CPU system shown in FIG. 2 has CPU 5, peripheral LSI circuit 8, and SDRAM 7. CPU 5 serves as a main processor of the conventional CPU system. Peripheral LSI circuit 8 has selector 81, SDRAM interface 82, and internal circuit 83.
Selector 81 is a selector for relaying an exchange with CPU 5 to a selected one of SDRAM interface 82 and internal circuit 83. Specifically, when access is made from CPU 5 to SDRAM 7, selector 81 selects SDRAM interface 82, and when access is made from CPU 5 to internal circuit 83, selector 62 selects internal circuit 83.
Internal circuit 83 is a circuit for realizing the functions of peripheral LSI circuit 8, and has a structure that may differ depending on the application of peripheral LSI circuit 8. Internal circuit 83 may have a processor therein. SDRAM 7 is connected to peripheral LSI circuit 8 by SDRAM interface 82, and can be accessed from CPU 5 via peripheral LSI circuit 8.
In the conventional CPU system shown in FIG. 2, selector 81 switches over access from CPU 5 based on the address contained therein to allow CPU 5 to access SDRAM 7 that is connected to peripheral LSI circuit 8.
It is an object of the present invention to provide a CPU system which is of a low cost and a reduced circuit scale and which includes a general-purpose peripheral LSI circuit and a high-speed memory for the peripheral LSI circuit.
To achieve the above object, a CPU system according to the present invention has a CPU, a peripheral LSI circuit, and an SDRAM.
The peripheral LSI circuit has a first interface connected to an SDRAM interface of the CPU and a second interface for accessing an external circuit. The peripheral LSI circuit determines whether access from the CPU via the first interface is directed to an internal circuit of the peripheral LSI circuit or the external circuit. If the access from the CPU is directed to the external circuit, then the peripheral LSI circuit stores a first bus signal from the first interface, adjusts the timing of the stored first bus signal and reads the first bus signal to generate a second bus signal having a rate which is at least twice the rate of the first bus signal, and accesses the external circuit from the second interface with the second bus signal. The SDRAM is connected to the second interface and accessible by the second bus signal.
Since the first interface is the same as the interface of the SDRAM, the CPU system can be constructed of a general-purpose peripheral LSI circuit that can be connected to a CPU having an interface with the SDRAM.
Because the peripheral LSI circuit adjusts the timing of access to the SDRAM, the CPU is capable of accessing the SDRAM with the same timing that it would access an SDRAM directly connected to the CPU.
According to one aspect of the invention, the internal circuit can access the SDRAM while bus arbitration is being carried out between the internal circuit and the SDRAM interface. As the internal circuit of the peripheral LSI circuit can access the SDRAM, the CPU system can employ a unified memory architecture. Because the second interface has a rate that is at least twice the rate of the first interface, the bandwidth of the memory for the peripheral LSI circuit is at least twice the bandwidth of the main memory for the CPU.
According to one aspect of the invention, a double data rate SDRAM takes the place of the SDRAM.
According to another aspect of the invention, there is also provided a peripheral LSI circuit connectable to a CPU for realizing predetermined functions, comprising an internal circuit, a selector, a timing adjusting circuit, and an SDRAM interface.
The internal circuit realizes the predetermined functions. The selector determines whether access from the CPU is directed to the internal circuit or an external circuit. The selector reads data from or writes data in the internal circuit if the access from the CPU is directed to the internal circuit. The selector sends the access from the CPU as a first bus signal if the access from the CPU is directed to the external circuit. The timing adjusting circuit stores the first bus signal and reads the stored first bus signal with predetermined timing to generate and output a second bus signal having a rate which is at least twice the rate of the first bus signal. The SDRAM interface accesses an SDRAM connected as the external circuit with the second bus signal from the timing adjusting circuit.
According to one aspect of the invention, in the peripheral LSI circuit, the internal circuit comprises an access circuit for accessing the SDRAM and an arbitration circuit for carrying out bus arbitration between the access circuit and the SDRAM interface.
According to one aspect of the invention, in the peripheral LSI circuit, a double data rate SDRAM is connected as the external circuit in place of the SDRAM.
The above and other objects, features, and advantages of the present invention will become apparent from the following description with reference to the accompanying drawings which illustrate examples of the present invention.